A latch is a storage element comprising two phases: a transparent phase during which the input values are copied onto the output and a storage phase during which the output state is maintained whatever the input state.
Generally, a storage element of CML latch type is formed of several branches, each branch comprising a charge component connected to an output terminal. The output terminal is connected to a current source common to the branches. Complementary logic input signals are applied to the control terminals of switches arranged in each branch.
A latch capable of operating under a power supply voltage smaller than that commonly used for the technology in which the circuit is manufactured has already been provided. An example of such a latch is described in U.S. Pat. No. 7,336,114. A disadvantage of the known latch is the presence, in each branch, of three transistors in series. The corresponding cumulated voltage drops adversely affect the power supply voltage decrease. It would be desirable to overcome the above shortcoming and further to accelerate the switching of a CML latch.